报告时间：9月23日 14:00
报告地点： 理科大楼B1002
报告名称：Logic time in real-time embedded design
报告摘要:
We study the use of Multiform Logical Time, as embodied in Esterel/SyncCharts and Clock Constraint Specification Language (CCSL), for the specification of assume-guarantee constraints providing safe driving rules related to time and space, in the context of Automated Driving Assistance Systems (ADAS). The main novelty lies in the use of logical clocks to represent the epochs of specific area encounters (when particular area trajectories just start overlapping for instance), thereby combining time and space constraints by CCSL to build safe driving rules specification. We propose the safe specification pattern at high-level that provide the required expressiveness for safe driving rules specification. In the pattern, multiform logical time provides the power of parameterization to express safe driving rules, before instantiation in further simulation contexts. We present an efficient way to irregularly update the constraints in the specification due to the context changes, where elements (other cars, road sections, traffic signs) may dynamically enter and exit the scene. In this way, we add constraints for the new elements and remove the constraints related to the disappearing elements rather than rebuild everything. The multi-lane highway scenario is used to illustrate how to irregularly and efficiently update the constraints in the specification while receiving a fresh scene.
报告人简介:
Prof. Robert de Simone is the Research Director at INRIA, scientific leader of the Aoste research team. From 2009 to 2013 he has been awarded a CNRS research grant in LIAMA and at Tsinghua University. His main research interests are Semantics and implementation of Synchronous Reactive formalisms, Verification tool design, associated algorithmic methods and Concurrency Theory.